
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DriverMotores is
    Port ( CLK : in  STD_LOGIC;
           Numero_Pasos : in  STD_LOGIC_VECTOR(31 downto 0);
           salidar : out  STD_LOGIC_VECTOR (3 downto 0);
           salidal : out  STD_LOGIC_VECTOR (3 downto 0);
           Interrupcion : out  STD_LOGIC);
end DriverMotores;

architecture Behavioral of DriverMotores is

COMPONENT SMotor 
    PORT ( CLK : in  STD_LOGIC;
			  sentido : in std_logic;
			  Numero_Pasos : in STD_LOGIC_VECTOR (29 downto 0);
			  Interrupcion : out STD_LOGIC := '0';
           Ss : out  STD_LOGIC_VECTOR (3 downto 0) := "0000"
			 );
END COMPONENT;




COMPONENT Retardo 
    PORT ( CLK : in  STD_LOGIC;
           CLK_out : out  STD_LOGIC
			 );
END COMPONENT;

signal x : std_logic;
signal clkaux : std_logic;
begin


ret : Retardo PORT MAP (
								CLK => CLK,
								CLK_out => clkaux
							   );

MR : SMotor PORT MAP (
									CLK => clkaux,
									sentido => Numero_Pasos(31),  -- cero adelante 1 atras
									Numero_Pasos => Numero_Pasos(29 downto 0),
									Interrupcion => Interrupcion,
									Ss => salidar
								);   --Secuencia de pulsos
									 
ML : SMotor PORT MAP (
									CLK => clkaux,
									sentido => Numero_Pasos(30),  -- cero adelante 1 atras
									Numero_Pasos => Numero_Pasos(29 downto 0),
									Interrupcion => x,
									Ss => salidal
								);   --Secuencia de pulsos



end Behavioral;

